My Projects
Complete Projects
High-Speed Link Design
Design and simulation of a 28 Gb/s link with transmitter FIR, CTLE, and bang-bang CDR. Focus on eye diagram optimization and ISI reduction using MATLAB/Simulink.
Digital CDR
Implementation of a digital SERDES with CDR loop, PRBS generation, frame recovery, and error counting. Verified in simulation and on FPGA with stable recovery.
5.4GHz VCO for PLL
Design of a 5.4 GHz VCO for PLL use, focusing on frequency tuning, phase noise reduction, and stable locking performance.
Reinforcement Learning In Satellite Communications
Applied reinforcement learning to optimize modulation, coding, and power allocation for adaptive satellite communication under changing channel conditions.
Current Projects
I have no currently active projects