My Projects
This page showcases four projects: two current ones I’m actively working on, both academically and personally, and two completed projects from my coursework.
Complete Projects
High-Speed Link Design
Design and simulation of a 28 Gb/s digital link incorporating transmitter FIR, receiver CTLE equalization, and timing recovery. The project focuses on eye-diagram optimization, ISI reduction, and clock/data recovery using a bang-bang CDR. MATLAB and Simulink were used to model the channel and verify system performance.
Digital CDR
Implementation of a complete digital SERDES system with a clock-and-data-recovery (CDR) loop. Includes PRBS generation, frame recovery, and error counting. The system was functionally simulated and deployed on a DE1-SoC FPGA, achieving stable phase alignment and error-free data recovery.
Current Projects
5.4GHz VCO for PLL
Design and characterization of a voltage-controlled oscillator operating at 5.4 GHz for use in a phase-locked loop (PLL). The project explores frequency tuning, phase noise optimization, and integration with PLL control circuits to maintain stable locking.
Reinforcement Learning In Satellite Communications
Exploration of reinforcement learning algorithms for adaptive signal processing in satellite communication systems. The project investigates automated modulation, coding, and power allocation strategies to optimize link reliability under varying channel conditions.